Exemplary embodiments relate to a semiconductor device and a method of manufacturing the same and, more particularly, to a non-volatile memory device having a three-dimensional (3-D) structure and a method of manufacturing the same.
A non-volatile memory device retains data stored therein even though the supply of power is stopped. As an increase in the degree of integration of two-dimensional (2-D) structured memory devices fabricated on a silicon substrate as a single layer is reaching physical limits, a 3-D non-volatile memory device in which memory cells are stacked in a vertical direction to the silicon substrate has been developed.
The structure of the conventional 3-D non-volatile memory device and features thereof are described in detail with reference to FIGS. 1 and 2.
FIGS. 1A to 1C are cross-sectional views illustrating a method of manufacturing the conventional 3-D non-volatile memory device. Particularly, FIGS. 1A to 1C are cross-sectional views of a non-volatile memory device of a U-shaped channel type in which strings are arranged in a U shape.
As shown in FIG. 1A, an insulating layer 11 is formed on a substrate 10, and a conductive layer 12 is formed on the insulating layer 11. The conductive layer 12 is used to form the pipe gate of a pipe transistor.
A first trench is formed by etching the conductive layer 12, and a first sacrificial layer 13 is formed in the first trench. The first trench is used to form a U-shaped pipe channel.
First interlayer insulating layers 14 and first conductive layers 15 are alternately formed on the resulting structure in which the first sacrificial layer 13 is buried. The first conductive layers 15 are used to form word lines.
A second conductive layer 16 and a second interlayer insulating layer 17 are formed on the first interlayer insulating layers 14 and the first conductive layers 15. The second conductive layer 16 is used to form the select gates of select transistors.
A pair of second trenches coupled to the first trench is formed by etching the second interlayer insulating layer 17, the second conductive layer 16, the first interlayer insulating layers 14, and the first conductive layers 15. The second trenches are used to form the channel of memory cells and the channel of the select transistors.
As shown in FIG. 1B, the first sacrificial layer 13 exposed under the pair of second trenches is removed.
Next, a charge blocking layer, a charge trap layer, and a tunnel insulating layer, hereinafter collectively denoted by reference numeral 18, are formed on the inner surface of the first trench and the pair of second trenches. A channel layer 19 having a central region opened is formed on the charge blocking layer, the charge trap layer, and the tunnel insulating layer 18. Accordingly, a U-shaped channel, including the pipe channel formed in the first trench and a pair of first channels formed in the pair of second trenches, is formed.
As shown in FIG. 1C, an insulating layer 20 is buried in the opened central region of the U-shaped channel. The insulating layer 20 is recessed to a specific depth, and conductive plugs 21 are formed in the recessed regions. The conductive plugs 21 are formed of polysilicon layers doped with N type impurities of a high concentration. The gates of the select transistors overlap with the conductive plugs 21, thus forming a junction doped with the N type impurities of a high concentration.
The erase operation of the 3-D non-volatile memory device constructed as above is performed in a depletion mode in which holes generated due to Gate Induced Drain Leakage (GIDL) in the junction are used in the erase operation. That is, the erase operation is performed in such a manner that the holes generated by GIDL are moved along the channel layer 19 and subsequently injected into the charge trap layers of the memory cells. Accordingly, in order for the conventional 3-D non-volatile memory device to adequately perform an erase operation, a sufficient number of holes are to be generated. To this end, the degree of overlap between the gates of source select transistors and the junction is to be properly controlled. If the source gate excessively overlaps with the junction, leakage may occur in the source select transistors.
FIG. 2 is a cross-sectional view of the conventional 3-D non-volatile memory device. Features of the conventional 3-D non-volatile memory device are described with reference to FIG. 2.
In the conventional 3-D non-volatile memory device, as described above, the conductive plugs 21 doped with impurities of a high concentration are formed on the upper part of the U-shaped channel, and the erase operation is performed in the depletion mode.
The conductive plugs 21 are formed by depositing a polysilicon layer and subsequently implanting the ions of impurities or depositing polysilicon doped with impurities of a high concentration. This process has the following features.
First, it is difficult to etch the insulating layer 20 buried in the opened central region of the channel. Here, in selectively etching, for example, only the insulating layer 20 without damaging the existing peripheral layers in the recess process, it is difficult to control the etching amount of the insulating layer 20. Accordingly, the insulating layers 20 of a plurality of strings may have irregular depths as shown in FIG. 2. In this case, the characteristic of the memory device is deteriorated because the conductive plug 21 irregularly overlaps with a source gate.
Second, if the ions of impurities are implanted after the polysilicon layer is deposited, it is not easy to control the diffusion of the impurities. If the ions of the impurities are implanted into the conductive plugs, process control is difficult because the diffusion of the impurities is to be controlled in a vertical direction, not a horizontal direction. Accordingly, controlling the overlap of the source gate and the junction is difficult.
Third, if polysilicon doped with impurities of a high concentration is to be deposited, the commercialization of the process, which is not frequently used, is difficult.
Fourth, if the erase operation is performed in the depletion mode, there is a variation of the erase speed between adjacent word lines or adjacent strings, and the swing characteristic of a select transistor deteriorates.